Performance Metrics

• Device R, C (pdf)
• Device Size (pdf)
• Device Delay (pdf)
• Device Power (pdf)

Device Level Design Tools

• Spice Simulator
• VLSI CAD tools - Layout, Floorplanning, Placement and Routing, Physical Verification (LVS/DRC/ERC)

Performance Metric

• Gate Area (pdf)
• Gate Delay (pdf)
• Gate Power (pdf)

Design Issues

• Clock
• PLL & DLL
• I/O

Transistor Level Design Tools

• Spice

Performance Metric

• Gate Count
• Path Delay (pdf)
• Switch Activity (pdf)

Design Issues

• Static Timing Analysis
• Scan and Boundary Scan Cells
• Formal Verification

Gate Level Design Tools

• Verilog
• VHDL
• Static Timing Analysis
• Formal Verification

Performance Metric

• Estimation of
  • Gate Count
  • Critical Path
  • Power
• Latency
• Throughput

Design Issues

• Partitioning and Coding Style
• Constraining Designs
• Optimizing Designs
• Design for Test (DFT)
• Pre-layout & Post-layout Simulation

RTL Design Tools

• Verilog
• VHDL
• Logic Synthesis

Background: Tiny CPU Examples

• (Instruction Set)
• (Data Path)
• (Control Path)

• Processors (pdf)
• Memories (pdf)

- Cache Memory

Readings (pdf)

Cache Note (pdf)

See also Content Addressable Memory (pdf), Address Partition (pdf), Cache Mapping (pdf)

- Virtual Memory

Readings (pdf)

- DRAM

Readings (pdf)

See also RAM Structure (pdf), RAM Timing (pdf), FPGA RAM (pdf)

• Interconnecting Buses

- AMBA AHB & APB

Readings (pdf)

• CISC, RISC, VLIW, Dataflow (1.pdf)
• CPU, DSP, GPU, NPU (2.pdf)
• MCU, ASIP, TTA (3.pdf)

Design Issues

• Memory Hierarchy
• Storage and I/O
• Instruction Level Parallelism
• Data Level Parallelism
• Thread Level Parallelism

Design Tools

• ADL (Architecture Design Language)

- LISA, EXPRESSION, nML, ArchC

• SystemC TLM (Transaction Level Modeling)

Typical SOC's

• Embedded System
• MPSOC
• NoC

Design Issues

• Transaction Level Modeling
• Hardware Software Partition
• Hardware Software Co-simulation
• Integration of Hardware IP Blocks
• Integration of Software IP Modules
• FPGA Based Emulation Platform

Design Tools

• High-Level Synthesis
• HVL (High-Level Verification Language)

- SystemC Verifcation (SCV) (See "SystemC programming in plain view")

- SystemVerilog

• Mixed Signal

- VHDL-AMS

- Verilog-AMS

- SystemC-AMS

HW/SW Design Examples : Traffic Controller Design

• HW/SW Implementation Overview (pdf)

Implementation in Hardware

• RTL Design Examples (pdf)
• Gate Level Design Examples (pdf)
• Transistor Level Design Examples (pdf)

Implementation in Software

• SW Implementation Without an OS (Bare Machine)

- Overview (pdf)

- Micro-controller Programming (pdf)

• SW Implementation with an RTOS (pdf)

RTL / Logic Level Design

• Logic Synthesis
• Logic Simulation
• Logic Timing Verification
• Logic Power Verification
• Test Synthesis
• Test Verification
• Testbench
• Code Coverage
• Equivalence Check
• Timing Verification
• Design Constraint
• STA (Static Timing Analysis)
• Scan Chain
• Back Annotation
• ATPG (Automatic Test Pattern Generation)

• See also SoC Design and Modelling Greave's Tutorial
  

Physical Design

• Floorplanning
• Placement
• Routing
• Power Network
• Clock Distribution
• Physical Verification
• DRC (Design Rule Check)
• DV (Design Verification)
• GV (Geometry Verification)
• LVS (Layout Versus Schematic)
• SV (Schematic Verification)