Tante Emma Analysis
In this section we want to analyse our Tante Emma Processor in a more abstract way. We want to show features acourding to the Computer Architecture VO.
Instruction Set Architecture
Our Tante Emma is a Register Register / load store architecture. One Instruction has 16 bit width and has different types of opcode width. Tante Emma has 28 opcodes with 8 bit and 8 opcodes with 4 bit. We have 16 registers whereas reg0 is always zero and reg15 is the return-address memory for procedure calls. The 14 registes left are general purpose registers. For more details see our ISA description.
ISA Design Hint for the LU
When ISA design is done for the practical unit, we recommend to write the assembler demo programms at the beginning of the ISA design phase. So you can decide better which instructions are needed for the ISA and which are useless. So you can reduce the number of instructions of your ISA, to have for example a fixed opcode width, which is easier to implement.
Pipelining
Our Processor has 4 pipelinestages.
- Instruction Fetch
- Instruction Decode
- Instruction Execution and Memory(LD/ST)
- Write Back (Registers)
Structual Hazards
We are using a Harvard architecture to avoid a bootle neck with 2 seperate memorys for instruction and data.
Data Hazards
- Read After Write (RAW)
To avoid RAW hazards, we do forwaring.
- Write After Read (WAR)
We do in order execution. We also do LD or ST only in stage 3.
- Write After Write (WAW)
We do in order execution. We also do LD or ST only in stage 3.
Cache
We have a write back cache with only one block. We have a simple instruciton and Data cache but we learned from other groups that the Rams are fast enough to reach a f_max of the processor of about 50 MHz, in our design with cache we also reach a f_max of about 50 Mhz. We want to annotate that the information about the MHz of the processor was from Quartus II Timeanalysis. For a real timeanalyisis, this has to be done with a hardware measurement.