Features

• Single core 16-bit RISC processor
• Harvard architecture
• 36 instructions
• 4 pipeline stages
• 14 16-bit GPRs
• reg0 --> zero register
• reg15 --> return address register
• 16-bit internal and 16-bit external bus
• 4 bit(for branch and LDIs) and 8 bit(for others) opcode width
• Little Endian number format

Instruction Set

Arithmetic and Logic Instructions

Instruction	Operation	Opcode	Flags	Format Type	Description
ADD rA, rB	rA ${\displaystyle \leftarrow }$ rA + rB	0b00100001	C,Z	4	Adds both registers without Carry and stores the value in rA. If the result is 0x0000 then the Z flag is set otherwise reseted. If there was a Carry from the MSB of the result the C flag is set, otherwise cleared.
ADC rA, rB	rA ${\displaystyle \leftarrow }$ rA + rB + C	0b00000001	C,Z	4	Adds both registers with Carry and stores the value in rA. If the result is 0x0000 then the Z flag is set, otherwise cleared. If there was a Carry from the MSB of the result the C flag is set, otherwise cleared.
SUB rA, rB	Ra ${\displaystyle \leftarrow }$ rA - rB	0b00000010	C,Z	4	Subtracts rB from rA and stores the result in rA. If the result is 0x0000 then the Z flag is set, otherwise cleared. If the absolute value of rA was smaller than the absolute value of rB then the C flag is set, otherwise cleared.
SBC rA, rB	Ra ${\displaystyle \leftarrow }$ rA - rB - C	0b00000011	C,Z	4	Subtracts rB plus Carry from rA and stores the result in rA. If the result is 0x0000 then the Z flag is set, otherwise cleared. If the absolute value of rA was smaller than the absolute value of rB plus Carry then the C flag is set, otherwise cleared.
AND rA, rB	rA ${\displaystyle \leftarrow }$ rA ${\displaystyle \wedge }$ rB	0b00000100	Z	4	Logical AND between rA and rB and the result is stored in rA. If the result is 0x00 then the Z flag is set.
OR rA, rB	rA ${\displaystyle \leftarrow }$ rA ${\displaystyle \vee }$ rB	0b00000101	Z	4	Logical OR between rA and rB and the result is stored in rA. If the result is 0x0000 then the Z flag is set.
XOR rA, rB	rA ${\displaystyle \leftarrow }$ rA ${\displaystyle \oplus }$ rB	0b00000110	Z	4	Exclusive OR between rA and rB and the result is stored in rA. If the result is 0x0000 then the Z flag is set.
NEG rA	rA ${\displaystyle \leftarrow }$ 0x0000 - rA	0b00000111	Z,C	3	Two's Complement of rA is stored in rA. If the result is 0x0000 then the Z flag is set. The C flag is always set except the result is 0x0000, then the C flag is cleared.
INC rA	rA ${\displaystyle \leftarrow }$ rA + 1	0b00001000	Z	3	Increments rA and stores the result in rA. If the result is 0x0000 then the Z flag is set. The C flag is never set by this operations, therefore this operation can be used in loops.
DEC rA	rA ${\displaystyle \leftarrow }$ rA - 1	0b00001001	Z	3	Decrements rA and stores the result in rA. If the result is 0x0000 then the Z flag is set. The C flag is never set by this operations, therefore this operation can be used in loops.
CLR rA	rA ${\displaystyle \leftarrow }$ rA ${\displaystyle \oplus }$ rA	0b00001010	Z	3	Clears register rA and Z flag is set.
SET rA	rA ${\displaystyle \leftarrow }$ 0xFFFF	0b00001011	Z	3	Sets register rA to 0xFFFF and clears the Zero flag.

Branch Instructions

Instruction	Operation	Opcode	Flags	Format Type	Description
CALL rA	Stack ${\displaystyle \leftarrow }$ PC + 1, PC ${\displaystyle \leftarrow }$ rA	0b00001110	None	3	Call subroutine. In Register A there is the absolute value of the Jumpaddress. CALL pushes the current PC +1 onto the Stack and decrement the Stack.
JUMP rA	PC ${\displaystyle \leftarrow }$ rA	0b00001111	None	3	Jump. In Register A there is the absolute value of the Jumpaddress.
RET	PC ${\displaystyle \leftarrow }$ Stack	0b00010000	None	5	Return from subroutine
CMP rA, rB	rA - rB	0b00010001	Z,L,G	4	Compare
CMPSKIP rA, rB	if (rA == rB) then PC ${\displaystyle \leftarrow }$ PC + 2	0b00010010	None	4	Compare, skip if equal
BRZ label	if (Z == 1) then PC ${\displaystyle \leftarrow }$ PC + label	0b1010	None	2	Branch, if zero
BRNZ label	if (Z == 0) then PC ${\displaystyle \leftarrow }$ PC + label	0b1011	None	2	Branch, if not zero
BRL label	if (L == 1) then PC ${\displaystyle \leftarrow }$ PC + label	0b1100	None	2	Branch, if lower
BRNL label	if (L == 0) then PC ${\displaystyle \leftarrow }$ PC + label	0b1101	None	2	Branch, if not lower
BRG label	if (G == 1) then PC ${\displaystyle \leftarrow }$ PC + label	0b1110	None	2	Branch, if greater
BRNG label	if (G == 0) then PC ${\displaystyle \leftarrow }$ PC + label	0b1111	None	2	Branch, if G = 0

Data Transfer Instructions

Instruction	Operation	Opcode	Flags	Format Type	Description
MOV rA, rB	rA ${\displaystyle \leftarrow }$ rB	0b00010011	None	4	Copy Register rB into rA
LDIH rA, Immediate High	rA ${\displaystyle \leftarrow }$ Immediate High	0b1000	None	1	Load high Byte of Immediate into rA. The low Byte of rA is unchanged.
LDIL rA, Immediate Low	rA ${\displaystyle \leftarrow }$ Immediate Low	0b1001	None	1	Load low Byte of Immediate into rA. The LDIL instruction performs sign extention. This means that the Bit 8 of Immediate is transfered into Bit 16 to 9 of Regiser A. So it is possible to load a signed value ${\displaystyle \rightarrow }$ -127 with only one instruction. When we want to laod for example the unsigned value 0xFF, we have to perform the LDIH with 0x00 to override the leaden Fs caused by the sign extention.
LD rA, rB	rA ${\displaystyle \leftarrow }$ (rB)	0b00010100	None	4	Load
ST rA, rB	(rA) ${\displaystyle \leftarrow }$ rB	0b00010101	None	4	Store
IN rA, PIN_NR(rB)	rA ${\displaystyle \leftarrow }$ PIN_NR(rB)	0b00010110	None	4	In from I/O location, whereas the pinnumber is saved in rB.
OUT rA, PIN_NR(rB)	PIN_NR(rB) ${\displaystyle \leftarrow }$ rA	0b00010111	None	4	Out from I/O location, whereas the pinnumber is saved in rB.
POP rA	SP ${\displaystyle \leftarrow }$ SP + 1, rA ${\displaystyle \leftarrow }$ Stack	0b00011000	None	3	Pop register from Stack; The Stack Pointer is pre-incremented by 1 before POP.
PUSH rA	Stack ${\displaystyle \leftarrow }$ rA, SP ${\displaystyle \leftarrow }$ SP - 1,	0b00011001	None	3	Push register on stack; The Stack Pointer is post-decremented by one after PUSH.
SPL rA	SP ${\displaystyle \leftarrow }$ rA	0b00011010	None	3	Stack pointer load. The value for the Stack pointer is saved in Register A

Bit and Bit-test Instructions

Instruction	Operation	Opcode	Flags	Format Type	Description
SHL rA	rA(n+1) ${\displaystyle \leftarrow }$ rA(n), rA(0) ${\displaystyle \leftarrow }$ 0, C ${\displaystyle \leftarrow }$ rA(7)	0b00011011	Z,C	3	Logical shift left
SHR rA	rA(n) ${\displaystyle \leftarrow }$ rA(n+1), rA(7${\displaystyle \leftarrow }$ 0, C ${\displaystyle \leftarrow }$ rA(0)	0b00011100	Z,C	3	Logical shift right
ASR rA	rA(n) ${\displaystyle \leftarrow }$ rA(n+1), n = 0,...,6	0b00011101	Z,C	3	Arithmetic shift right
ROL rA	rA(0) ${\displaystyle \leftarrow }$ C, rA(n+1) ${\displaystyle \leftarrow }$ rA(n), C ${\displaystyle \leftarrow }$ rA(7)	0b00011110	Z,C	3	Rotate left through Carry
ROR rA	rA(7) ${\displaystyle \leftarrow }$ C, rA(n) ${\displaystyle \leftarrow }$ rA(n+1), C ${\displaystyle \leftarrow }$ rA(0)	0b00011111	Z,C	3	Rotate right through Carry

Instruction Format

Pipeline

Our processor "Tante Emma" has 4 pipeline stages:

• Instruction fetch - Load command to the command buffer; increment PC
• Instruction decode - Initialize operands from registers; generate processor internal control signals
• Execute - ALU makes operation, calculation of a address in load/store commands
• Writeback - load/store, write result in register

Registers

Pin Numbers

For the OUT and IN operation we have to define a pinnumber. Use these pin numbers for the following pysical device.

UART RX TX

In this section we want to describe how to handle the UART within an assembler program.