 | |
| Developer(s) | Community |
|---|---|
| Initial release | August 2011 |
| Stable release | v22.1
/ December 30, 2022 |
| Written in | C++, Python |
| Operating system | Linux |
| License | Revised BSD License |
| Website | www |
The gem5 simulator is an open-source system-level and processor simulator. It is utilized in academic research and in industry by companies such as ARM Research, AMD Research, Google, Micron, Metempsy, HP, and Samsung.[1][2] Arm has developed further software called Streamline for developers working with gem5 which aims to present "a graphical view of system execution".[3]
History
The gem5 simulator was born out of the merger of m5 (CPU simulation framework) and GEMS (memory timing simulator).[4]
Features
gem5 is an event-driven simulator with multiple execution modes.[4]
- full-system emulation (simulating the whole OS) and syscall emulation (just user-space is emulated)
- multiple ISAs (Alpha, ARM, SPARC, MIPS, POWER, RISC-V, and x86 ISAs)[1]
- timing model for the full cache hierarchy with support for custom coherence protocols
- simplistic CPU, in-order CPU, out-of-order CPU
- serialize/deserialization from checkpoints
References
- 1 2 "gem5: About". Retrieved 14 November 2019.
- ↑ "Simulation Research and gem5". Davis Architecture Research. Retrieved 22 June 2022.
- ↑ "Streamline for gem5". Arm Developer. Retrieved 22 June 2022.
- 1 2 Binkert, Nathan; Sardashti, Somayeh; Sen, Rathijit; Sewell, Korey; Shoaib, Muhammad; Vaish, Nilay; Hill, Mark D.; Wood, David A.; Beckmann, Bradford; Black, Gabriel; Reinhardt, Steven K. (2011-08-31). "The gem5 simulator". ACM SIGARCH Computer Architecture News. 39 (2): 1–7. doi:10.1145/2024716.2024718. S2CID 195349294.
External links
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