< Computer Architecture Lab < SS2013 < Group3

BraveMIPS Instruction Set Architecture

BraveMIPS Instruction Set Format

The format of the 32bit MIPS I processor is kept:

Type-31-                                 format (bits)                                 -0-
Ropcode (6)rs (5)rt (5)rd (5)shamt (5)funct (6)
Iopcode (6)rs (5)rt (5)immediate (16)
Jopcode (6)address (26)

(same as on Wikipedia Page)

BraveMIPS Instruction Set

The instruction set is focused on integer-based instructions and it essentially consists of a subset of the MIPS Instruction Set (see the full set on Wikipedia, section "Integer"). Other instructions might be added as project progresses.

CategoryNameInstruction syntaxMeaningFormat/opcode/functNotes/Encoding
Arithmetic Addadd $d,$s,$t$d = $s + $tR02016adds two registers, executes a trap on overflow
000000ss sssttttt ddddd--- --100000
Subtractsub $d,$s,$t$d = $s - $tR02216subtracts two registers, executes a trap on overflow
000000ss sssttttt ddddd--- --100010
Add immediateaddi $t,$s,C$t = $s + C (signed)I816-Used to add sign-extended constants (and also to copy one register to another: addi $1, $2, 0), executes a trap on overflow
001000ss sssttttt CCCCCCCC CCCCCCCC
Multiplymult $s,$tLO = (($s * $t) << 32) >> 32;
HI = ($s * $t) >> 32;
R01816Multiplies two registers and puts the 64-bit result in two special memory spots - LO and HI. Alternatively, one could say the result of this operation is: (int HI,int LO) = (64-bit) $s * $t . See mfhi and mflo for accessing LO and HI regs.
Dividediv $s, $tLO = $s / $t     HI = $s % $tR01A16Divides two registers and puts the 32-bit integer result in LO and the remainder in HI.
Data Transfer Load wordlw $t,C($s)$t = Memory[$s + C]I2316-loads the word stored from: MEM[$s+C] and the following 3 bytes.
Store wordsw $t,C($s)Memory[$s + C] = $tI2B16-stores a word into: MEM[$s+C] and the following 3 bytes. The order of the operands is a large source of confusion.
Logical Andand $d,$s,$t$d = $s & $tR02416Bitwise operation and
000000ss sssttttt ddddd--- --100100
And immediateandi $t,$s,C$t = $s & CIC16-Leftmost 16 bits are padded with 0's
001100ss sssttttt CCCCCCCC CCCCCCCC
Oror $d,$s,$t$d = $s | $tR02516Bitwise or
Or immediateori $t,$s,C$t = $s | CID16-Leftmost 16 bits are padded with 0's
Exclusive orxor $d,$s,$t$d = $s ^ $tR02616
Nornor $d,$s,$t$d = ~ ($s | $t)R02716Bitwise nor
Set on less thanslt $d,$s,$t$d = ($s < $t)R02A16Tests if one register is less than another.
Set on less than immediateslti $t,$s,C$t = ($s < C)IA16-Tests if one register is less than a constant.
Bitwise Shift Shift left logicalsll $d,$t,shamt$d = $t << shamtR00shifts shamt number of bits to the left (multiplies by )
Shift right logicalsrl $d,$t,shamt$d = $t >> shamtR0216shifts shamt number of bits to the right - zeros are shifted in (divides by ). Note that this instruction only works as division of a two's complement number if the value is positive.
Conditional branch Branch on equalbeq $s,$t,Cif ($s == $t) go to PC+4+4*CI416-Goes to the instruction at the specified address if two registers are equal.
000100ss sssttttt CCCCCCCC CCCCCCCC
Branch on not equalbne $s,$t,Cif ($s != $t) go to PC+4+4*CI516-Goes to the instruction at the specified address if two registers are not equal.
Unconditional jump Jumpj CPC = PC+4[31:28] . C*4J216-Unconditionally jumps to the instruction at the specified address.
Jump registerjr $sgoto address $sR0816Jumps to the address contained in the specified register

BraveMIPS Assembler

The assembler is based around JFlex and CUP (Java implementations of a lexer and parser). Until now I have successfully "compiled" the lexer file, whose source is found here: /assembler/jflex/bravemips_scanner.l I still need to get the CUP-specific syntax to run and integrate the two.

NOTE: in the worst case scenario, I might implement a pure Java String manipulation-based assembler (if I will have problems with JFlex and CUP).

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