< Computer Architecture Lab

Project page for the course in summer 2011.

Group 1 AID

Nicolas Ingemann Borup

Jonas Andersen Dindorp

Cristian Pandele

Instruction Set 1

Summary and comparison between instruction sets of:

  1. MIPS
  2. ARM7
  3. LC3
  4. Zilog Z8

Document:

    Assignment1

    Architecture implementing decimal (AID)

    This page contains information about the implementation of a decimal processor in the course Advanced computer architecture on DTU

    Introduction


    Instruction set architecture

    We have several formats for the instruction set, as the operations needs different inputs

    Type 1:

    InstructionOpcodeDestination registerSource registerSource registerUsage
    add0001RdRsRtRd ← Rs + Rt
    mult0011RdRsRtRd ← upper part(Rs x Rt), Rd+1 ← lower part(Rs x Rt)
    sub1010RdRsRtRd ← Rs - Rt


    Type 2:

    InstructionOpcodeDestination registerSource registerSource registerUsage
    Immediate load0010RdimmimmRd ← imm


    Type 3:

    InstructionOpcodeDestination registerSource registerSource registerUsage
    shift left0111RdRsshamtRd ← Rs << shamt
    shift right1000RdRsshamtRd ← Rs >> shamt
    negation1011RdRsXXXRd ← -Rs
    load1110RdRsimmRd ← mem[Rs(imm)]
    store1111RdRsimmmem[Rd] ← Rs


    Type 4:

    InstructionOpcodeDestination registerSource registerSource registerUsage
    branch equal1100addressflag valueflag enabledif (flag value == ALU flags){next PC ← address}
    branch return1101addressflag valueflag enabledif (flag value == ALU flags){next PC ← address; push stack ← curr PC}


    Type 5:

    InstructionOpcodeDestination registerSource registerSource registerUsage
    jump to return0110XXXXXXXXXnext PC ← pop stack
    nop0000XXXXXXXXXno operation

    Group 2 FooBarBaz fighters

    Mark Ruvald Pedersen

    Laust Brock-Nannestad

    Jaspur Højgaard

    Rasmus Bo Sørensen

    Assignment I

    Summary and comparison between instruction sets of:

    1. PIC16F84 microcontroller
    2. ARM
    3. Intel 80x86

    ISA / CPU Design

    Document (Assignment II):


    UART Exercise (Assignment III)

    Group 3 [Newbies]

    Ioannis Chionidis

    Georgios Papanikas

    Xia Hua

    Henning Dietmar Weiss

    Document:

    Group 4

    Andreas Erik Hindborg

    Niklas Quarfot Nielsen

    Tobias Jeppe

    Kristoffer Lyder Andersen

    Assignment 1

    Summary of:

    1. ARMv7-M
    2. PIC
    3. x86
    4. POWER7

    Document: https://www.campusnet.dtu.dk/cnnet/filesharing/ViewFileHistory.aspx?ElementId=347459&FolderId=567165&FileId=2700363

    Group ??

    Caroline Johannsen

    Assignment I

    ...

    Leros

    Martin Schoeberl (no group - this is just a template ;-)

    An FPGA optimized tiny processor core for utility functions (e.g., SW UART). The challenge is to get the resources below 500 LC and use just 2 RAM blocks. The processor is named after the Greek island Leros where the architecture was designed. Details of the design can be found at the Leros processor page.

    Perhaps I will do this design along the course to see how much work the assignment actually is ;-)


    Group 6

    Dimitrios Kosmadakis

    Assignment I

    Summary of:

    1. Intel 4004
    2. Intersil 9100
    3. TMS 9900
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